Voltage-Island based Floorplanning in VLSI for Area Minimization using Meta-heuristic Optimization Algorithm

Floor planning is the primary step of the physical design in the Very Large Scale Integration (VLSI) design flow. It is used to estimate the chip area and wire length prior to the real placement of digital blocks and their interconnections. In the modern physical design of VLSI chips, it is essential to design the chip, which works with multi-supply voltages (MSV). To achieve power optimization, MSV circuits are partitioned into voltage islands (VI) where each island occupies an adjoining physical space and operates at one supply voltage. Since, floorplanning is a NP-hard problem, many optimization techniques were adopted in literature. In the proposed work, a new two step methodology is used for VI constrained fixedoutline nonslicing floorplanning based on meta-heuristic optimization algorithm, with the aim of reducing the total chip area. Here, a music-inspired Twin Memory Harmony Search (TMHS) is used as the meta-heuristic optimization algorithm. The experimental results show that our proposed approach provides efficient floorplanning with reduced area and wirelength. Experiments on MCNC benchmark circuits validate the effectiveness of our work. keywords: Floorplanning; Voltage-Island; Multi Supply Voltage; Harmony Search; Meta-heuristic Optimization; Very Large Scale Integration Introduction Floorplanning is the first step of the physical design in the VLSI design flow. It is an essential design step to estimate the chip area by considering the optimal placement of digital blocks and their interconnections. Each block consists of several hundreds or thousands of cells that perform a specific operation. The blocks are of rectangular shape with different aspect ratios. The blocks can be classified into two types based on their shape flexibility. They are hard blocks and soft blocks. Hard block has fixed width and height whereas soft block’s width and height can be varied as long as its aspect ratio is within the given range and its area is constant. The aspect ratio of a block is defined as the ratio between the height and the width of a block. To optimize the area of the chip, hard blocks are rotated then the width and height of soft blocks are modified such as without affecting the area of the block. The classical floorplanning methods normally handles only block packing to minimize the total chip area, but modern floorplanning methods could be devised as a fixed outline floorplanning. There are two types of floorplanning methods used in electronic design automation. They are slicing and nonslicing floorplan. In slicing floorplan, the whole block area is first partitioned into two slices of equal or unequal sizes using either a horizontal or vertical line then the individual blocks are again partitioned into by using either horizontal or vertical lines. This process continues until all the blocks are separated. This process of partitioning the block area is called slicing floorplan. The slicing floorplan is represented by a binary tree structure known as slicing tree. If a floorplan is obtained with no recursive through cuts, it is called nonslicing floorplan. Different techniques are used to represent the non-slicing structure of a floorplan. They are sequence pair [1], bounded sliceline grid (BSG) [2], O-tree [3] and B*-tree [4]. Classical floorplanning methods deal with the minimization of chip area by optimizing the module positions and their interconnections. In the modern physical design of VLSI era, it is essential to design the chip with small size which consumes less power. In order to reduce routing complexity of power nets, modules with identical voltage source have better to be placed together. This also can reduce the difficulty in insertion of level shifters. MSV circuits are partitioned into Voltage Islands (VI) where, each island occupies an adjoining physical space and operates at one supply voltage. Thus, a designer usually groups up the modules powered by the same voltage source as a VI and ensures that the created groups do not violate timing constraint or induce routing congestion. The VI driven floorplanning problem is more difficult than the classical floorplanning problem. The objective of any optimization algorithm is to minimize or maximize the objective function. Optimization algorithms are mostly used in all engineering problems. Since VLSI floorplanning is a NP-hard problem which is to be optimized, in this work music-inspired Twin Memory Harmony Search (TMHS) algorithm is used for VLSI floorplanning. The rest of this paper is organized as follows: the next section reviews the recent and related work in the field of VLSI floorplanning. Then the proposed framework is described, followed by the experimental setup and discussion of obtained results. Finally the conclusion is given with possible scope for further explorations. International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 5 (2016) pp 3469-3477 © Research India Publications. http://www.ripublication.com 3470 Related Works Many researchers have focused on optimization algorithms for floorplanning in both slicing and non-slicing structures. O-tree representation is proposed by Guo et al [3] based on a nonslicing floorplan. Ma et al [5] implemented the boundary constraint algorithm for general floorplan by extending the Corner Block List (CBL) algorithm, which is an efficient topology representation for non-slicing floorplan. For non-slicing VLSI floorplanning, a Genetic Algorithm (GA) has also been presented by Gwee and Lim [6]. Xu et al [7] applied Tabu search algorithm to solve module placement problem. Initially, all the modules are merged into some clusters according to the ratio-connectivity of circuit modules. The placement of the large modules is represented by sequence-pairs. The searching of optimal solution of placement is performed by the Tabu search algorithm. Tang and Sebastian [8] scheduled a GA to tackle the VLSI floorplanning problem using O-tree representation. Particle swarm optimization (PSO) [9] was introduced into the floorplanning problem to find the potential optimal placement solution. This structure is unable to solve problems that optimize the area and wirelength simultaneously. A memetic algorithm (MA) for a non-slicing and hard-module VLSI floorplanning problem was presented by Tang and Yao [10]. Pradeep Fernando and Srinivas Katkoori [11] proposed a multi-objective genetic algorithm for floorplanning that simultaneously minimizes area and total wirelength. The proposed genetic floorplanner is the first to use nondomination concepts to rank solutions. Chen et al [12] proposed a novel floorplanning algorithm based on Discrete PSO (DPSO) algorithm, in which integer coding based on module number was adopted. The principles of mutation and crossover operator in the GA are also incorporated into the proposed PSO algorithm to achieve better diversity and escape from local optima. Chen et al [13] used a PSO algorithm for floorplanning where area and wirelength are considered as the fitness function. A new heuristic method [14] was proposed that applied hybrid simulated annealing (HSA) to represent a non-slicing floorplan with an objective function by restricting the area and wirelength. Sengupta et al [15] used a sequence pair approach to represent non-slicing floorplans with a smaller search space. Shanavas et al [16] proposed a method that combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. Chen et al [17] proposed a co-evolutionary multi objective particle swarm optimization (CMOPSO) algorithm to solve a VLSI floorplanning problem which is a multi objective combinatorial optimization and has been proved to be a NPhard problem. The algorithm imports the concept of coevolutionary algorithm and elitist strategy into basic PSO algorithm. It takes both the layout area and total interconnection wirelength into consideration simultaneously. An approach based on iterative prototypes optimization with evolved improvement (POEMS) algorithm was proposed by Singha et al [18]. It uses a genetic algorithm (GA) for local search and adopted a non-slicing structure B* tree for the placement of rectangle modules. Hoo et al [19] used a VOAS (Variable – Order Ant System) for area optimization based on the ant algorithms. This method uses the models that are derived from the observation of real ants’ behavior, and uses as a source of inspiration for the design of novel algorithms for the solution of optimization and distributed control problems. Sivaranjani and Senthil Kumar [20] proposed a smart decision-making PSO-GA based hybrid method for thermal-aware non-slicing VLSI floorplanning. B*-tree representation is used in this method. VLSI floorplanning is a NP-hard problem. The solution space will increase exponentially with the growth of circuits scale, thus it is difficult to find the optimal solution by exploring the global solution space. Proposed Methodology Harmony Search Algorithm The Harmony Search (HS) method is a meta-heuristic optimization algorithm proposed by Geem et al [21]. It mimics a musical improvisation process in which the musicians in an orchestra/band try to find a perfect state of harmony through musical improvisations. When musicians compose harmonies, they usually try various possible combinations of the music pitches stored in their memory. This algorithm was designed to mimic the way a musician uses short-term memory and the past experiences to lead his/her to the note that results in the most pleasing harmony when played together with the other musicians. HS is easy to implement and can easily be applied to solve almost any problem that can be designed as the minimization or maximization of an objective function. This kind of efficient search for a perfect state of harmonies is related to the procedure of finding the optimal or near-optimal solutions for a problem. When solving a particular problem, each musician is considered as a decision variable. So, the perfect harmony means the global or near-global solution. In HS, each musician corresponds to a decision variable in the solution vector of the problem and also represents a dimension in the search space. Each musician (decision variable) has a different instrument whose pitch range corresponds to a decision variable’s value range. A solution vector, also called an improvisation, at certain iteration corresponds to the musical harmony at a particular period, and the objective function corresponds to the audience’s aesthetics. New improvisations are based on earlier remembered good ones which are stored in the data structure called the Harmony Memory (HM). A new solution is improvised by using three rules. They are (a) Play what he/she exactly knows (memory consideration) (b) Play by slightly adjusts the pitch (pitch adjustment) and (c) Play a new composition (random selection). The main control parameters of HS algorithm are harmony memory (HM), Harmony Memory Size (HMS), Harmony Memory Considering Rate (HMCR), Pitch Adjusting Rate (PAR), and Bandwidth (BW). Here, HM is a memory location where all the solution vectors are stored; HMCR and PAR are parameters that are used to improve the solution vector. Harmony memory and Improvisation The core data structure of HS is a matrix of the best solution vectors called the harmony memory (HM). The number of International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 5 (2016) pp 3469-3477 © Research India Publications. http://www.ripublication.com 3471 vectors that are concurrently processed is known as the harmony memory size (HMS). It is one of the algorithm’s parameters that have to be set manually. Memory is structured as a matrix with each row represents a solution vector and the final column represents the vector’s fitness value. In the HS algorithm, X represents the harmony and f(X) denotes the melody of harmony X. In a N-dimensional problem, the HM would be represented as follows. Before optimization starts, the HM is initialized with HMS randomly generated solution vectors. Based on the problem, these vectors can also be randomly chosen around a seed point that may represent an area in the search space where the optimum is most likely to be found [22]. Each decision variable is improvised individually, and any one of the three rules can be applied for any variable. The harmony memory consideration rate (HMCR) is one of the HS parameters that must be manually chosen. It controls how often the memory (HM) is taken into consideration during improvisation. For standard HS, memory consideration means that the decisions variable’s value is chosen directly from one of the solution vectors in the HM. A random number is generated for each decision variable. If it is less than the HMCR, the memory is taken into consideration; else, a value is randomly chosen from the range of possible values for that dimension. The pitch adjustment rate (PAR) is set during initialization, and it controls the amount of pitch adjustment done when memory consideration is used. Another random number is generated. If it is smaller than the PAR, the improvised value is pitch adjusted using the Equation (1). (1) where x’new is the new pitch-adjusted value, xnew is the old value chosen using memory consideration, rand() is a random value between −1 and 1, and BW is the Bandwidth parameter. It is the maximum variation in pitch adjustment and is one of the parameters that must be manually set. Once a new value has been improvised, the memory is updated by comparing the new improvisation with the vector in the memory with the lowest fitness. If the new improvisation has a higher fitness, it replaces the vector with the lowest fitness. This process of improvisation and update continues iteratively until some stopping criterion is fulfilled, or the maximum number of iterations is reached. Steps in HS Step 1: Initialize the problem and algorithm parameters Step 2: Initialize the Harmony Memory (HM) Step 3: Improvisation In this step, New Harmony vector is generated based on three rules, namely, memory consideration, pitch adjustment and random selection. The value of a design variable can be selected from the values stored in HM with a probability HMCR. It can be further adjusted by moving to a neighbor value of a selected value from the HM with a probability of pitch adjusting rate (PAR), or, it can be selected randomly from the set of all candidate values without considering the stored values in HM, with the probability of (1 HMCR). Step 4: Update HM If the new harmony vector is better than the worst vector, based on the objective value and/or constraint violation, the new vector will replace the worst one. Step 5: Termination criterion HS algorithm is terminated if the stopping criterion (maximum number of improvisations) has been met; else steps 3 and 4 are repeated. Pseudocode of Harmony Search Algorithm begin Set the objective function of the given problem as f(x), x=(x1, x2, ..., xd) Generate initial Harmony memory and initial harmonics (random values) Define pitch adjusting rate (rpa), pitch limits and bandwidth Define harmony memory accepting rate (raccept) while ( traccept), choose an existing harmonic randomly from HM else if (rand>rpa), adjust the pitch randomly within the limits else generate new harmonics via randomization end if Accept the new harmonics (solutions) if they are better end while Find the current best solutions end HS method is a random search technique. It has been successfully applied in many engineering fields. It does not need any earlier domain knowledge, such as the gradient information of the objective function. It requires fewer mathematical requirements and does not entail initial value settings of the decision variables. As it uses stochastic random searches, derivative information is also not necessary. HS algorithm generates a new solution, after considering all the existing solutions. HM stores the past search experiences and plays an important role in its optimization performance. HS has the attractive advantage of algorithm simplicity. Twin Memory Harmony Search algorithm HS has good performance but one drawback it holds is the single harmony memory for optimization process. Studies show that the HS method usually suffers from a slow search speed. To overcome this drawback, we propose a Twin Memory Harmony Search algorithm for VLSI floorplanning. In the proposed TMHS, two harmony memories are used. Both the Harmony Memories are initialized with HMS randomly generated solution vectors. New improvisations are based on the past remembered good ones which are stored in the HM. Since two harmony memories are used in this method, the value of a design variable can be selected from the values stored in both the HM with a probability HMCR. Instead of HMS initial solutions, by using the proposed International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 5 (2016) pp 3469-3477 © Research India Publications. http://www.ripublication.com 3472 method 2*HMS solutions are generated. From that, HMS best solutions are taken into consideration. The Figure 1 shows the flowchart of proposed TMHS. Figure 1: Flowchart of TMHS algorithm Fitness function Evaluation For the TMHS algorithm in floorplanning, each musician corresponds to a possible solution. The main objective of the floorplanning is to minimize the total chip area and wire length. The formula for calculating the total area of the chip that contains ‘i’ modules is given in Equation (2). (2) The wirelength of the i module with respect to the other modules in the given floorplan can be calculated by using Half-Perimeter Wirelength (HPWL). It is defined as half the perimeter length of the smallest bounding box that encloses all pins. Let us consider net i, connected with different terminals, a small rectangle box that encompasses all the terminals chosen. The HPWL of the net i can be calculated according to the Equation (3). (3) Here, Xmax and Xmin are the maximum and minimum xcoordinates of the HPWL bounding box of the net. Ymax and Ymin are the maximum and minimum y-coordinates of the HPWL bounding box of the net. The total wirelength can be calculated using the formula denoted in Equation (4). (4) A fitness function must be devised for each problem to be optimized. It is a designed function that measures the goodness of a solution. It is essential to estimate how good a possible solution is relative to other potential solutions. The fitness function is responsible for performing this evaluation and returns a fitness value. In each iteration, the priority of the solution vector is ranked according to the fitness value calculated using the fitness function. By maximizing/minimizing the fitness values in each generation, the global optimum value could be found. The fitness function for the proposed method is given in Equation (5). (5) Here α and β values are treated as the weighting factors. In this work α and β values are taken as 0.8, 0.2 and 0.5, 0.5. Experimental Results The proposed method utilizes fixed-outline with VI constraint for non-slicing floorplanning. The experiments in this study make use of MCNC [23] (Microelectronics Center of North Carolina) benchmark circuits for the proposed floorplanners. Simulations have been carried out for the MCNC benchmark circuits namely apte, ami33, hp and xerox. Table 1 shows the characteristics of MCNC benchmark circuits. The simulation programs were written in MATLAB version R2013a and the results were obtained on a Pentium i3, 2.7 GHz and 2GB memory system configuration. Table 2 gives the Parameters and their values of the optimization algorithms used in this method. Table 3 shows the details about the number and hard and soft modules considered in this work. Table 1: Characteristics of MCNC benchmark circuits Name of the Benchmark Circuit No. of Modules No. of Nets No. of I/O Pad No. of Pins Area (mm) apte 9 97 73 287 46. 56 ami33 33 123 42 522 1. 1564 hp 11 83 45 309 8. 83 xerox 10 203 2 698 19. 35 Table 2: Parameters and their values of TMHS algorithm Parameter Value HMCR 0. 9